1. Field of the Invention
The present invention relates in general to a chemical mechanical polishing (CMP) process in semiconductor manufacturing. In particular, the present invention relates to a method of reducing the pattern effect in a CMP process, a method of eliminating the dishing phenomena after a CMP process, and a CMP rework method.
2. Description of the Related Art
Chemical mechanical polishing (CMP) has been popularly applied to the planarization treatment of conductive wires in logic device processing and contact window processing, and especially, to the fabrication of sub-130 nm interconnects in ultra-large scale integration (ULSI) silicon device. With respect to a damascene technique, the desired process requires removal of the metal (such as copper) overburden followed by the over-polishing to ensure that all residual copper is completely removed. However, during the CMP process, if an area ratio of the conductive wire to the insulating layer is too large, a pattern effect arises, resulting in the phenomenon known as “dishing”. As shown in FIG. 1, when performing a CMP process on a conductive wire 103 of a large pattern area, polishing rates of the conductive wire 103 and an insulating layer 101 are different, as a result, the center area of the conductive wire 103 exhibits a severe dishing effect as shown by a dotted line 104. As the dishing phenomenon occurs, sheet resistance (RS) varies, and as a result the electrical properties deteriorate. Therefore, the pattern effect is undesirable.
During a CMP process, a substrate is subject to three polishing stages for, as is shown in FIGS. 2a to 2d. The planarization stage denoted by “P” shown in FIG. 2a begins with polishing and ends when the copper layer surface becomes substantially planar. The transition stage denoted by “T” shown in FIG. 2a begins after the copper layer surface is substantially planar and ends when the dishing phenomenon begins. The duration of the transition stage is often very short. The dishing stage denoted by “D” shown in FIG. 2a begins when the dishing phenomenon first occurs until the end-point is detected by the CMP device. FIG. 2b shows a schematic view of a general substrate profile at the beginning of a CMP process, that is, at the beginning of the planarization stage. There is an original step height which gradually decreases as the substrate is polished. FIG. 2c shows a schematic view of the general substrate profile near the beginning of the transition stage. The surface of the substrate is almost planar but the dielectric layer has not been exposed, thus polishing continues. The transition stage can act as the operating window for a polishing machine. This stage is very short and when the polishing approaches and reaches the interface between the conductive layer and the dielectric layer, the polishing machine receives an end-point signal and stops. The substrate, however, is often at the dishing stage, as shown in FIG. 2d, and exhibits a serious dishing phenomenon caused by the pattern effect.
Furthermore, the end-point for polishing is often erroneously reached due to faulty signal collection. Generally, more than 20% polished wafers have end-point failure and become abnormal substrates reported by CMP machines. The conductive layer (for example, Cu) thickness is often incorrectly reported due to the narrow operating window, which results from the very short transition stage. This leads to additional complications in maintaining the desired metal topography and requires CMP rework for failed wafers. It is difficult, however, to find an adequate recipe to rework wafers because the under-polish levels of polished wafers are event-related. As more wafers require CMP rework, lower wafer yield is obtained. Thus, a transition stage of increased duration is desirable for improving the detection of end-point failure cases. In addition, the problems of the dishing phenomena caused by over polishing after a CMP process and the abnormal wafers reported by CMP machines need to be solved.
U.S. Pat. No. 6,461,225 B1 discloses a method of manufacturing an integrated circuit to avoid dishing of the copper, wherein copper is deposited inside the trench defined in a substrate, a copper alloy layer is formed over the surface of the copper wherein the copper alloy is of the formula Cu—M and M is selected from the group consisting of Ni, Zn, Si, Au, Ag, Al, Mn, Pd, Pb, Sn, or blends thereof, and the resulting structure is planarized. The copper layer is deposited to fill the trench at a level approaching the top surface of the underlying wafer, but not overfill the trench, and the deposition of copper alloy comprising metal other than copper increases the process complexity.
U.S. Pat. No. 6,251,786 B1 discloses a method of treating the surface of a copper dual damascene structure on the surface of a semiconductor substrate, thereby reducing the dishing effect and erosion of copper surfaces used in interconnect metal, wherein the copper surface of said dual damascene structure is polished and recessed down to the surface of the barrier layer, a thin film is deposited over the surface of said recessed dual damascene, and, part of said deposited thin film is then removed. The thin film, which contains Si3N4 or any other dielectric material, may cause the interconnect to have an increased electrical resistance.
Hence, there is a need for a better method to reduce the pattern effect in a CMP process, a method to eliminating the dishing phenomena, and a CMP rework method.